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The Next Step - Datapath Configuration | Cypress Semiconductor

The Next Step - Datapath Configuration

Now that it's been determined that the there are two datapath operations that need to be performed, the Datapath Configuration Tool can be used to configure a datapath that performs those functions.

The Datapath Configuration Tool is only installed with PSoC Creator Beta 5 if you chose to do a Complete install.  If you chose to do a Typical install it was not installed.  You can go back and change your installation to Complete and it will add the Datapath Configuration Tool.  With the next PSoC Creator release the Datapath Configuration Tool will be made part of the typical installation.

To start using the Datapath Configuration Tool you need to have a Verilog file to work with.  I'll assume that you've gone through the training on creating a Verilog component.  Refer to my post on "Creating Your Own Components".

Launch the Datapath Configuration Tool from the Start menu at Cypress->PSoc Creator 1.0->Component Development Kit->Datapath Configuration Tool.  Make sure that the Verilog file that you've created in PSoC Creator is saved.  The Datapath Configuration Tool will read this file in and then later it will be saved back with changes, so you need to be careful to only edit in one place at a time and to save when switching between which editor is changing the file.  Use the File->Open menu item to open the Verilog file.

At this point you wouldn't have created any datapath instances in your Verilog, so there are no datapaths to configure yet.  Use Edit->New Datapath... to create a datapath.  Give it a name and select the 8-bit datapath cy_psoc3_dp8.  Your new datapath will show up in the Configuration selection with the instance name you chose followed by "_a(8)".  The "_a" is the extension given to the least significant byte of a datapath and the "(8)" indicates this is used as part of an 8-bit datapath.  If this had been a wider datapath then there would have also been an "_b" configuration and possibly an "_c" and "_d".  Each byte of the datapath has its own configuration.  Only an 8-bit datapath is needed to implement a UART.

There are two pieces to the configuration: Dynamic and Static.  The Dynamic configuration is the CFGRAM area at the top of the Datapath Configuration Tool.  The Static portion is the rest of the configuration.

In the Verilog code the two dynamic operations have been labeled LOAD and SHIFT and assigned addresses 0 and 1 respectively.  The usage of the dynamic configuration is controlled by the control store address (cs_addr port of the datapath instance) which has been assigned to the cfg signal.

Using the pictures from the previous post, the dynamic configuration can be filled out to match the operations:

Only the first two configurations are populated since the others are unused.  In the LOAD configuration the only operation to perform is to load A0 from the F0 FIFO.  This is done by setting the A0 write source (A0 WR SRC) to F0.  The ALU function being performed doesn't matter.  For the Shift operation the ALU operation is simply to PASS the value in A0 (SRCA is used for the PASS operation) and then shift it right (SR SHIFT operation).  Then that result is written back to A0 (ALU as the A0 WR SRC).

There are several columns that have not been used that I'll mention here.  CFB EN is only used for CRC type operations, so this is typically disabled.  The CI SEL, SI SEL, and CMP SEL select which static configuration to use for carry input, shift input and comparison.  Each of these has an A and a B choice and then in the static configuration there is a configuration for A and B.  For this component only a shift is used and only one configuration is needed, so A is chosen and then static configuration for A is configured.

The Static configuration is the same for all 8 of the dynamic operations with the exception that for several of the operations there is an A and a B configuration that can be selected dynamically.  I'll address more of the static fields with other component examples.  For this component the fields of importance have been highlighted:

Many of these settings are the default values, but the values of each of these settings applies to this application:

  • DEF SI: The default shift in value can be either 0 or 1.  Here it is configured as 0.
  • SI SELA: The A shift In selection is being used in the dynamic configuration.  It is configured to use the default shift in value which is 0.  This isn't actually important for this application since 8 bits are shifted out and then the value that remains is not used.  This setting however will result in A0 having 0 in it once it has shifted out the 8 bits.
  • SHIFT SEL:  Selects whether the shift out signal is taken from the left or from the right.  This can be confusing since the dynamic configuration has already selected that a shift right will be implemented.  The dynamic configuration does determine the final ALU result which is written back.  This static confguration determines whether the LSB or MSB is sent out on the shift out (so) port.  This application is using the shift out bit as the bit to transmit, so it must be configured to take the LSB (shift right).  Note that the shift out is still the LSB or MSB even when no shift operation is being performed.  That can be useful for some applications where the LSB or MSB is needed, but a shift is not desired.
  • F0 INSEL: This selects the direction of the FIFO.  In this case the FIFO value should come from the CPU or DMA (BUS).
  • FIFO ASYNC: This controls whether the FIFO block fill level signal needs to be synchronized.  Setting this to ASYNC means that this datapath is not running on BUS_CLK and needs the synchronizer to be added.  This will add a single flip-flop clocked on the datapath clock.  This makes the block status synchronous to the datapath clock and means that timing will be easier to meet in the logic that uses this signal.  This selection should normally be set to ASYNC as shown here.

With the configuration complete the Verilog file is written back with this configuration added to the instance for the datapath by using File->Save.  If you reload the Verilog in PSoC Creator you can see that the datapath instance has a set of parameters as part of the instance.  These are a direct reflection of the configuration information selected in the Datapath Configuration Tool.  These could have been entered by hand, but the Datapath Configuration Tool allows this large amount of configuration data to be entered and read in a graphical manner.

With the next post I'll take a look at connecting up the datapath to the rest of the Verilog.

 

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