Direct Digital Synthesis with an Indexed DMA | Cypress Semiconductor
Direct Digital Synthesis with an Indexed DMA
If any of you have cracked open the Technical Reference Manual for PSoC 3 and looked at the DMA section, you would have noticed that there are many different supported modes. The mode that was used for my previous post by the nameof Intro to DMA on PSoC 3 and PSoC 5 is called “Auto Repeat DMA”. There is another mode that is labeled “Indexed DMA”. That mode appears that it could be powerful, but you might wonder how it is actually done. In this mode a hardware component is used to generate either a source or destination address for a DMA transaction. This capability can be used to generate a sine wave like the Auto Repeat mode did, but in this case a hardware component is used to generate a sine wave of varying frequency that is controllable in small increments at run time.
The implementation of an indexed DMA uses one or more DMA Transaction Descriptors (TDs) to transfer an address from a component to another TD that performs the transaction of interest. In this example 3 TDs are used as shown:
The first two TDs read the address from the Phase Accumulator component. The third TD reads from that address and sends it to the DAC.
The Phase Accumulator is a custom hardware component that was built for this example and is included with the design. It uses the programmable digital logic in the UDB array to generate the address needed by the DMA. The implementation of this Phase Accumulator uses a 16 bit counter and a programmable increment value. The upper ten bits are used as the index into a 1,024 entry sine wave SRAM lookup table. The lower 6 bits allow for finer increments in the generated frequency. The result is a Direct Digital Synthesis implementation. The focus of this blog entry is the Indexed DMA functionality. Details about building hardware components will be addressed in future blog entries.
This example brings together the unique combination of capabilities of PSoC 3 and PSoC 5 (programmable digital, programmable analog and flexible DMA engine) resulting in a design that is fully controllable by the processor, but also fully offloads the processor.
You can see PSoC in action here and the design is attached for you to experiment further with the power of PSoC: IndexedDMA.zip