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Creating Your Own Components | Cypress Semiconductor

Creating Your Own Components

One of the more powerful aspects of PSoC 3 and PSoC 5 is the ability to use components that encapsulate both hardware and software functionality.  Cypress provides a large library of the most common components that you might need (I2C, UART, DAC), but there is no end to the possible components that PSoC 3 and PSoC 5 can support.  The Creator platform allows you to develop and use your own components using the same methodology as Cypress engineers.

There are 3 levels of components that a user might want to develop:

  1. Schematic Component
  2. Verilog Component
  3. Datapath Component

Each level gets progressively more involved and more powerful.  A schematic based component provides a hierarchical schematic capability.  Here you can combine any of the components in the current library and also encapsulate the APIs that go with that combination.  With a Verilog based component you have the ability to pull in more complex unique digital content and take direct advantage of the PLDs built into PSoC 3 and 5.  The capability to do either Schematic or Verilog based components is in Creator today.  The third level, datapath based components, adds to a Verilog component the usage of the datapath resources in PSoC 3 and 5.  With datapaths you can create denser designs and more flexibily communicate between your hardware component and the CPU.  The ability for customers to take advantage of datapaths in their own components will be made available in Creator with the Beta 5 release due out later this year.

In order to get you started on the right track, I've developed several training classes that each include:

  • Video
  • Slides
  • Example Projects

They are all posted on the Cypress website under the Design Support tab, then Technical Training, then On-Demand Training, or you can skip directly there with the following links:

 Then I'll build on this training with some more examples and insights here on the blog.

Comments

rolf's picture

Hi Brad,

I noticed PSoC Creator 2.1 generates a somewhat different verilog module definition than your example in the PSoC Creator 113 class.

This if from your example:

module Count4ByN (
count,
clock,
reset
);
output [3:0] count;
input clock;
input reset;
parameter N = 1;

And this is generated from Creator 2.1:

module Count4ByN (
output [3:0] count,
input clock,
input reset
);
parameter N = 1;

I had to change the definitions manually in order to make it work. However by the definitions will be overwritten if the Verilog is generated again.

Can you tell me the best solution for this?

And thank you for the nice classes you've made! I still have to follow your 2xx series of classes to make me understand the most probably best part of PSoC3/5.

Hope to see you again at one of the FAE conferences!

Regards,
Rolf - Gold Design Partner

bjbu's picture

Rolf - Sorry for my slow reply, I missed your comment until now. The issue that you are having is with the needing the count signal to be of "reg" type. With the new way that these are automatically handled, that can't be done in the merge region which leads to your problem. My recommendation is to use a different signal in the merge region that is declared as a reg type. Do all the work in your module using that signal. To get from that signal to the count signal use an assign statement. All that can be in the merge region, it doesn't use any more logic and operates identically to the original implementation.

- Brad

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