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Count7 Added to the PSoC Sensei Library | Cypress Semiconductor

Count7 Added to the PSoC Sensei Library

The PSoC Sensei Component Library now has the 7-bit down counter hardware called Count7 encapsulated into a component.  The latest library is available here: PSoCSenseiLibrary122710.zip

This component uses some optional pins, so I'll use this component as an example to explain how that is implemented.  There are several modes of operation for the Count7 and depending on the mode the enable (en) and load (load) signals may or may not be present.

This is implemented on the component by two parameters on the symbol.  These parameters are passed to the hardware where they provide the parameters to the count7 primitive instance.  The “Hardware” attribute of the parameter controls whether the parameter is passed to the Verilog implementation.

These parameters are also used to control the presence of the pins on the symbol.  To control the presence of a pin select the pin in the symbol editor.  Then right select and choose “Format Shape”.  In this dialog the Visibility of the pin can be controlled using an expression that uses parameter values.  A default value needs to also be provided.  The pin is always present for the Verilog instance, so this becomes the value used when the pin is not present.

Next time you need a 7-bit or smaller down counter you have another implementation option with the Count7.

Comments

danaaknight's picture

Brad, due to new release of Creator and the change of counters to fully synch I may have to
abandon PSOC 3. My problem is quite simple, I need a 32 bit asynch counter, no other features
other than reset, that can count to > 50 Mhz. Basically a very simple freq counter is all I need.
I start with a reset input and gate counter input with a 1 sec gate. I assume my only way out
is to learn Verilog and do it from scratch ? Not6e if I had to compromise I could limit counter to
30 Mhz max, but thats bottom line.

Regards, Dana.

bjbu's picture

Dana - I'd like to understand your issue in a little more detail, because a see a couple of problems in trying to resolve it. The first issue is that a 32-bit UDB based counter simply can't count that fast (regardless of sync versus async issue). 30MHz is also a stretch, but in the ball park. To handle this issue I would need some form of a prescaler so that the 32-bit counter could operate at a slower speed. The second issue is the need to operate in a synchronous fashion. The reason for this is that the datapath based elements interact with other elements of the device (the CPU in particular) and asynchronous operation for the general purpose counter just presents too many problems.
A potential solution could be to use an asynchronous prescaler that then feeds a synchronous counter. This could be designed to handle the asynchronous requirement and the performance requirement. The prescaler would need to be implemented with macrocells or the count7 and the communication between it and the rest of the design would have to be managed properly. Could you describe exactly what you want to do with the counter. In particular I'm interested in your needs to capture the bits that would be in the prescaler.
- Brad

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