Count7 Added to the PSoC Sensei Library | Cypress Semiconductor
Count7 Added to the PSoC Sensei Library
The PSoC Sensei Component Library now has the 7-bit down counter hardware called Count7 encapsulated into a component. The latest library is available here: PSoCSenseiLibrary122710.zip
This component uses some optional pins, so I'll use this component as an example to explain how that is implemented. There are several modes of operation for the Count7 and depending on the mode the enable (en) and load (load) signals may or may not be present.
This is implemented on the component by two parameters on the symbol. These parameters are passed to the hardware where they provide the parameters to the count7 primitive instance. The “Hardware” attribute of the parameter controls whether the parameter is passed to the Verilog implementation.
These parameters are also used to control the presence of the pins on the symbol. To control the presence of a pin select the pin in the symbol editor. Then right select and choose “Format Shape”. In this dialog the Visibility of the pin can be controlled using an expression that uses parameter values. A default value needs to also be provided. The pin is always present for the Verilog instance, so this becomes the value used when the pin is not present.
Next time you need a 7-bit or smaller down counter you have another implementation option with the Count7.