Completing the UART Verilog Implementation | Cypress Semiconductor
Completing the UART Verilog Implementation
Now that the datapath has been created, there is just a little more work required to complete the Verilog implementation of the high speed transmit only UART.
The datapath configuration tool created the instance of the datapath and it was used to fill out all the parameters that were needed to configure it. The tool didn’t however connect the datapath up to the rest of the Verilog implementation. That part is done from the PSoC Creator editor. With the datapath fully configured and saved, it can be loaded back up in the editor in Creator. The top part of the instance is all the parameters that were populated by the Datapath Configuration Tool and they should be left untouched. The bottom part of the instance is where all the ports of the instance are connected. Typically only a small portion of these will be connected. In this case the following need to be connected:
- clk: A clock must always be provided. This is the clock that everything in the datapath is clocked by. Because the registers of the datapath also are read and written by the CPU or DMA which is operating using BUS_CLK, the clock provided as the clock should also be synchronous to BUS_CLK.
- cs_addr[2:0]: This is the control store address bus. It selects which of the 8 possible dynamic configurations are executed for each clock period. This will need to be connected to something other than the default 3’b0 unless only one operation is needed. For this component it is connected to the cfg signal that has been decoded from the State register.
- so: Shift Out is the signal that provides the shifted out value that is transmitted as the data for the UART.
- f0_bus_stat: This is one of the status signals for the F0 FIFO. The F0 FIFO is the FIFO that is providing the data to be sent by the UART. When a FIFO is configured for input (input into the datapath) this signal indicates that the FIFO is not full. That information is needed by the CPU or DMA to prevent them from overflowing the FIFO. For the CPU this is passed via a Status register. For the DMA this signal is passed to the DMA controller directly as the drq signal on the component.
- f0_blk_stat: This is the other status signal for the F0 FIFO. This signal indicates that the FIFO is empty. It is used by the state machine to know when to move on and transfer the next byte of data.
Here is the Verilog connectivity for the datapath.
There are two remaining pieces to this component: Clocking and the Status Register. Many datapath components will also have a Configuration Register. This component only implements the transmit side of the UART, so it doesn’t need an enable bit which would require a Control Register. As long as nothing is sent from the CPU/DMA, then it just waits for data.
As mentioned earlier, datapath components need to be driven by a clock that is synchronous to BUS_CLK. There are some rare exceptions to this rule, and it is much more difficult to create a component that isn’t synchronous to BUS_CLK. This component is designed with the expectation that the clock is synchronous to BUS_CLK. There is a special component that has multiple clocking uses called UDB Clock Enable. I’m not going to discuss all the uses for this component here, but I will show this specific use. If a clock signal is passed as an input to this component and it is configured to have it’s sync_mode set to TRUE, then the clock signal that comes out of this component will always be synchronous. PSoC Creator will analyze the input clock. If it is already synchronous, then this component will just pass the input clock to the output clock. If the input clock were not synchronous, then PSoC Creator would create a double flip-flop synchronizer circuit. This would cause the output clock to be synchronous to BUS_CLK. The input clock used is the clock provided to this component. The output clock is then used throughout the implementation of this component.
For the overall implementation of this component including the APIs, the CPU will need some information about the current status of the component. In this case a status register is used to provide this information from the hardware. In addition to just providing the status it may also be desired to generate an interrupt to the CPU, so a specific type of Status register that can generate an interrupt called a statusi is used. This type of status register can have up to 7 bits. Each of those bits can be masked. If any of the bits are high and the mask for that bit is high, then an interrupt is generated. Each of the bits can be transparent or sticky. The transparent bits provide the direct value of the signal to the CPU. In sticky mode the signal is captured at every rising edge of the clock. If it is high at that time, that high is retained (sticky) until it is cleared by the CPU reading the status register.
There are two pieces of status information that are provided by this component. The first is whether the FIFO is not full. As long as this is active the CPU can continue to send data. The second piece of information is whether the component is idle. The idle indication can be used to determine when the transmission of a message has been fully sent by the hardware of the UART.
The parameters passed to the Status register are:
- cy_force_order: This must always be set to 1. It forces PSoC Creator to maintain the ordering of the bits exactly as described. This is the only mode currently supported.
- cy_md_select: This selects on a bit by bit basis whether the bit is transparent (0) or sticky (1). In this case the bits are all transparent.
- cy_int_mask: This is the interrupt mask. This is typically set by default to 0 which disables interrupts for all bits. Later if desired an API can write the mask to another value.
Below is the instance of the status register used for this component.
That completes the hardware implementation of this component.
If you’d like to build your own component or you have an idea for an interesting design, take a look at the Cypress ARM Cortex-M3 PSoC 5 Design Challenge.