When Vref is not equal to Vref | Cypress Semiconductor
When Vref is not equal to Vref
Over the last couple of years I have been asked several questions about the reference system in PSoC3 and PSoC5. The common assumption is that when you place a Vref component in your schematic and set the reference to 1.024 volts, you will get 1.024 volts +/-0.1% at room temperature. Unfortunately this is not true. What you will actually get is a voltage that is not exactly 1.024 volts, but with an offset of several mVolts. But the PSoC datasheet says that the Vref is trimmed to within +/- 1mV, what's the deal? To understand this, you need to first understand the PSoC3/5 Reference Tree. Below is a simplified version.
Notice that on the upper left hand side there is a bandgap voltage reference that generates about 1.2 volts. Its output is buffered then fed into a resistor network to create a voltage near 1.024 volts. This output is connected to the input of several reference buffers that drive different analog blocks including comparators, opamps, the DelSig ADC (Upper Right), and the SC/CT blocks. During calibration, the output of the DelSig ADC’s reference buffer is measured to get exactly 1.024 volts +/- 0.1%, while the bandgap voltage is adjusted. This means that only the DelSig ADC’s reference is the only true calibrated reference. The input to the other reference buffers may be off by several mVolts to start with. Each reference buffer will also have its own input offset as well. If the input offset of all the references buffers were the same, then all the references would match, but this is unlikely. The input offset of all the buffers will most likely vary from buffer to buffer. This is why a reference may not be exactly 1.024 volts and why references will not all be the same.
By Mark Hastings