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Manchester Code

Manchester Code:

 

 
Manchester Code is a digital encoding format in which symbol ‘1’ is represented by a falling edge (high followed by low) and symbol ‘0’ is represented by a rising edge (low followed by high). Both the high and low pulses have equal width which is equal to half the bit period.
 
Figure 1
 
The advantages of Manchester code are:
  • Single signal conveys the data and clock information
  • Self synchronization
A Manchester encoder embeds the clock information with data in a simple way: each bit is transmitted with a transition at the middle of bit time. For ‘1’, it is 1 to 0 and for ‘0’ it is from 0 to 1.
An example of a Manchester Code is shown in Figure 2.
Figure 2
 
 

Manchester Encoder:

 

 
There are several ways of designing a Manchester Encoder. But doing it “The PSoC Way” requires just an SPI Master and an XOR Gate.
 
When the SPI Master is configured to operate in Mode 0 where the data is setup on falling edge of the clock and data is latched on the rising edge. The idle state of the clock output is low.
The MISO pin of SPI Master is set to low so that the idle state of the MOSI is low.
 
The MOSI of SPI Master is XORed with the clock to obtain Manchester Encoded data.
  • When the MOSI is “low”, the XORed output follows the clock. Hence there is a transition from low to high (rising edge = ‘0’).
  • When the MOSI is “high”, the XORed output is an inverted version of clock. Hence there is a transition from high to low (falling edge = ‘1’).
The output thus obtained is in Manchester encoded format.
The waveform shown in Figure 3 demonstrates the same.
 
Figure 3
 
The schematic shown in Figure 4 represents the implementation in PSoC 3.
 
Figure 4
 
The encoded output is to be fed to the Manchester Decoder unit.
 
 
 

Manchester Decoder:

 

 
The decoder implementation used here is not based on the direction of the mid bit edge (rising or falling edge), but it is based on the fact that the bit value is present during the first half of bit time, prior to the transition edge. If a delay of 3/4th bit is triggered by the incoming mid bit transition, the value captured at the end of the delay represents the next bit value.
 
Figure 5
 
The clock has to be recovered from the incoming Manchester encoded data signal. As mentioned before, a delay unit is used to obtain the actual data signal. This signal when XORed with the Manchester encoded data gives the Clock.
 
The waveform is shown in Figure 6.
 
Figure 6
 
In the figure above, Polarity_invert represents the decoded data, and the XORed value shown as the last waveform is the recovered clock.
It can be observed that the Manchester Decoded data can be read upon sampling the data on rising edge of the Recovered Clock. This is demonstrated in the Figure 7.
 
 
Figure 7
 
A Manchester Decoder block diagram is as shown below:
 
 
Figure 8
From the block diagram, it can be seen that the main functional units are:
  • An XOR Gate – Used to derive the Clock which in turn triggers the Delay unit.
  • A Delay Unit – Produces a delay of 3/4th bit period.
  • A D Flip-Flop – Used to hold the Serial data out.
The schematic of the Manchester Decoder implementation in PSoC 3 is shown in Figure 9.
 
Figure 9
 
A PWM Component is used to generate a delay of 3/4th of the bit period. When this period has elapsed, a pulse is generated which is fed to the clock input of the D Flip-Flop. The Flip Flop is updated upon this clock input.
 
 

Working:
To demonstrate the process of Manchester Encoding and Decoding, the project was built on PSoC 3.
 
The Manchester encoder was used to send an 8-bit sequence 0x34. The Manchester decoder unit was able to recover clock from the encoded data and also decode the value.
The oscilloscope snap-shot is shown in Figure 10.
 
Figure 10
 
Yellow = Manchester encoded data
Blue = Decoded Serial data (0x34)
Pink = Recovered Clock
 
From the waveform, it can be seen that when the serial output data is sampled on the rising edge of the recovered clock, the output obtained is 0b00110100 which is 0x34.
 
However, it should be noted that the first bit transmitted should be 0. Hence, the encoded sequence should be appended by 0 in its first position.
This is used for providing the synchronization to determine the second bit (which is the beginning of the actual sequence).
If the first bit is ‘1’, then the decoded output will be in 1’s complement format of the expected output.
 
 

PSoC Value:
The advantages of using PSoC for this design are:
  • Simplicity in designing of the encoder - Just an SPI Master with an XOR Gate are the only requirements.
  •  Implementation of Decoder in Hardware – Manchester decoder uses a D Flip-Flop and an XOR which are implemented in hardware. The PWM Component has to be initialized at the beginning of code. Then, no CPU intervention is required for its further operation.
The snap-shot of the code looks like this:
 
 
 

Summary:

 

 
Manchester encoder / decoder was implemented in PSoC 3. The output obtained was as expected.
 
By Gautam Das

 

Comments

Gautam Das's picture

In addition to the output received, we can use a Shift Register Component available in the component catalog to obtain the decoded value.
The clock to the Shift Register Component is the Clock obtained from the decoder unit.
The Shift register will act as a SIPO (Serial In Parallel Out), in which the CPU will read the parallel value from the Shift Register after every 8 clocks.

rol's picture

Hi,
i am working the last 5 years with manchester encoding / decoding, using an RFID 125kHz system and sorry, a Silabs F8051xxx µcontroller. In this case the max baudrate is apprx. 4.8 kbits/s. I like to have a much higher baudrate. Your solution looks very nice and I will implement in a PSoC-3 first touch development system. Hopfully to rich a baudrate nearly 100kbits/s. Or schould I better wait until Cypress has its library updated with an Manchester decoder/ encoder core, including an 8 bit receive and transmit register plus an IRQ ?

P.S. I am still looking for an implementation of an LPC interface (Intel low pin count interface, 33MHz)

Happy new Year
ROL

khivabrothers2_2616551's picture

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