Digital Design Best Practices | Cypress Semiconductor
Digital Design Best Practices
For me, one of the most fascinating aspects of PSoC 3 and PSoC 5 is the Universal Digital Blocks (UDBs). They greatly enhance the computational capabilites of PSoC 3/5, to the point where in many cases you can offload most if not all of the CPU's functionality, sometimes leaving the CPU with literally nothing to do after initialization. They contain as many as 24 8-bit datapaths for simple computations - add, subtract, increment, decrement, bitwise AND, OR, XOR, and shift.They also contain as many as 48 small PLDs which can be used to implement combinatorial logic and state machines. The UDBs add a whole dimension to MCU programming that may be new to many designers.
To help you learn about and effectively use the UDBs, we're launching a series of new application notes that cover the topic in great detail. The first one, AN81623, PSoC 3/5 Digital Design Best Practices, is intended to introduce designers, especially firmware engineers, to the field of digital design and how it is done with PSoC 3/5. Forthcoming application notes will give detailed instruction on the use of PLDs, datapaths and other UDB features.
AN81623 gives a brief introduction to digital hardware design theory and then describes the digital subsystem in PSoC 3 and PSoC 5. It also describes best practices for digital design using PSoC Creator, and shows how to use static timing analysis (STA) report files.
So this application note should help you more effectively use the digital components available to you right now - Counter, Timer, PWM, Shift Register, Quadrature Decoder, and more. And with the Lookup Table (LUT) component you should easily be able to build simple state machines. Then watch for more advanced application notes, coming soon, that will show how to implement your own complex digital designs in the PSoC 3/5 UDBs.
To download this new application note "Digital Design Best Practices" click on this link, AN81623.
By Mark Ainsworth