## UART Clock Accuracy Requirement in PSoC 1

When using the UART user module in the PSoC 1, the most important parameter for the UART is the clock. The user module data sheet says the clock to the UART should be 8x the baud clock. So, for a 9600 baud rate, the clock to the UART should be 8 x 9600 = 76.8KHz.

In PSoC 1, this clock has to be derived from the SysClk or SysClk * 2. Let us take SysClk for this case and assume a SysClk of 24Mhz. To get a frequency of 76.8KHz from 24MHz, the required divider is 312.5. Unfortunately, we cannot have a fraction in the divider and have to round off to 312 or 313. For a divider of 312, the resulting clock is 76.923KHz. This gives rise to a plethora of questions. Is this clock accurate enough? Will I get bit errors because of the deviation in the clock? What is the maximum tolerance allowed in the clock to UART?

Before we get into the answer to the question, let us first derive the maximum error allowed in the UART clock. Picture below shows the UART RX line and the internal 8x clock. The UART data transfer starts with a Start bit, 8 data bits, optional parity bit and ends with a Stop bit.

Ideally, the Receiver samples the RX line at the mid-point of every bit.  If the UART clock has 0% error, then the sampling will happen exactly at mid-point of the Stop bit.  But as the UART clock will have a tolerance, depending on the +ve or ve error on the UART clock, the sampling will happen earlier or later than the mid-point on every bit.  This error keeps accumulating and will result in the maximum error on the Stop bit.  Ideally the maximum error allowed on the Stop bit would be + ½ a bit, ie, 50% of the bit time.  But practically, if we sample earlier or later by 50% of the bit time, we will be sampling at the bit transition.  For systems that have higher bus capacitance and higher rise and fall times, this will create a problem.

So, allowing for rise and fall times at 20% of the bit time, we have a room of +40% of the bit time in the Stop Bit.  The tolerance allowed on the UART clock is +40% / (No. of Bits).  For an UART with one Start bit, 8 data bits and one Stop bit, the maximum error allowed on the clock would be +4%.  This 4% tolerance has to be split between the devices on the either side of the UART bus.  For example, if a device on one side of the UART bus runs on a crystal at 100ppm, the device on the other side can have a clock tolerance of +3.99%.  Remember, this 4% also is again subject to system performance.  If you are running a very long cable and the UART at a very high baud rate, the rise and fall times may be more than 20% of the bit time and you will have lesser room for error.  AT lesser baud rates and shorter cables, you will have more room for error.

Now let us check the round off error introduced by the divider.  For a 9600 baud, we use a divider of 312 on the SysClk which results in a clock of 76.923KHz against the requirement of 76.8KHz.  The error introduced by this deviation is just 0.1% and is negligible.

The next contributor to the error budget is the tolerance of the clock source which is the IMO.  In most of the PSoCs (CY27x43, CY29x66, CY24x23, etc), the IMO has a tolerance of +2.5% over the full operating temperature.  This is well within the +4% tolerance.  Also, the PSoC boot.asm code writes a factory programmed trim value to the IMO trim register, which further reduces the error of the IMO to <1%.  So, clocking the UART from the IMO will not introduce any problem.

What about the devices which have IMO with a tolerance of >=4% (CY24x94, CY21x34 etc)?  In fact, when you place an UART component in the CY24x94 device, the Design Rule Checker gives a warning that to use an UART, the device should be connected to the USB bus.  When connected to the USB bus, the IMO gets synced to the USB clock and hence will become as accurate as the USB bus clock.  When not connected to USB bus, it runs at +4% tolerance and hence this warning.
For these devices various options may be considered.

1. What is the device on the other side of the UART? If the device on the other side of PSoC runs on a crystal, then the complete 4% error margin can be used by the PSoC.  Also, though the IMO is specified for an accuracy of >+4%, after the trim in boot.asm, it will be better than +2%.
2. What is the slowest baud rate that you can use in the system?  Lower the baud rate, the rise and fall times will occupy lesser part of the bit time and the tolerance of the UART bus will tend towards 5% and you get more room for error.
3. What is the shortest cable you can use?  Shorter the cable, lesser the bus capacitance.  This will reduce the rise and fall times and the tolerance will tend towards 5%
4. For the CY8C24x94, if you are not using the USB, then you may consider using other devices like CY8C27x43 or CY8C29x66.
5. Use an external 24MHz oscillator and connect this oscillator to P1[4].  In the Global Resources select P1[4] as the SysClk source.

With the above considerations, a robust UART communication can be built in PSoC 1.

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