High Resolution High Frequency PWM in PSoC4 BLE | Cypress Semiconductor
High Resolution High Frequency PWM in PSoC4 BLE
PWM1 is configured to have two 8 bit outputs, one channel with compare type Less and the other channel with compare type Less or Equal . PWM mode is set to Hardware Select . This implements a multiplexer between the two PWM channels selected by a hardware signal. This is the cmp_sel signal input in PWM1 which is driven by PWM2. While it was necessary to simultaneously start the two PWM channels in PSoC1, in PSoC4 BLE, as the PWM is one block simultaneous starting is automatically taken care of.
PWM2 is configured for single output, with a period of 255. Below picture shows the configuration windows for PWM2.
The code for the high resolution PWM is straightforward.
The HighResPWM_WritePUlseWidth function writes the most significant 8 bits of the compare value to the two channels of PWM1 and the least significant 8 bits of the compare value to the control PWM.
The duty cycle of the HighResPWM is given by:
Duty Cycle % = (Compare Value / 65536) * 100.
Following pictures show the output of the HighResPWM at 10% and 50% duty cycles.
So, I started with a minimum requirement of a 14 bit PWM with 4.4kHz, and ended up with a 16 bit PWM with 10x the frequency. Following is the digital resource usage of the HighResPWM.
The project file may be found below.