Handling Multiple GPIO Interrupts in PSoC 1 | Cypress Semiconductor
Handling Multiple GPIO Interrupts in PSoC 1
March 23, 2014
PSoC has a single GPIO interrupt vector which is common for all the GPIO pins. This poses some problems when interrupts are enabled on multiple GPIO pins. Let us discuss the problems introduced by this architecture and techniques to address these problems.
The interrupt logic of a GPIO cell is shown in figure below.
The PRTxICx registers set the type of interrupt (disabled, high, low and change from last read). The corresponding PRTxIE bit enables or disables the interrupt for the GPIO. When the interrupt is enabled in the PRTxIE register and if the interrupt condition as configured by PRTxICx occurs on the GPIO pin, the IRQ# line is asserted.
The IRQ# lines from all the GPIO cells are tied together. This creates a wired OR setup for the active LOW IRQ signal. The IRQ signal is considered edge sensitive for asserting and level sensitive for releasing the interrupt. i.e., the interrupt controller registers a GPIO interrupt when a falling edge is detected on the IRQ line, but will not register any interrupts till the IRQ line goes back to HIGH state. This creates problems in detecting multiple interrupts occurring simultaneously.
For example, consider the scenario #1 shown in figure below.
GPIO#1 is configured for high level interrupt whereas GPIO#2 is configured for low level interrupt. When GPIO#1 goes high, the IRQ line is asserted and the interrupt controller posts an interrupt. While GPIO#1 is high asserting the IRQ line, GPIO#2 too goes low asserting the IRQ signal, and goes high de-asserting it before GPIO#1 de-asserts the IRQ. As no change is registered on the IRQ line, the interrupt from GPIO#2 is not registered by the interrupt controller.
Now consider another scenario #2 shown in figure below.
In this case, GPIO#1 asserts the IRQ line. Before it de-asserts the IRQ line, GPIO#2 also asserts the IRQ line. GPIO#2 continues to assert the IRQ line even after GPIO#1 de-asserts. As there is no state change on the IRQ line, the interrupt controller does not register the interrupt from GPIO#2.
Well. How do we address these scenarios? Below are some techniques that can be used to overcome these situations.
1. As soon as a GPIO pin generates an interrupt, change the interrupt type of the GPIO (high to low or low to high). This will immediately disable the GPIO from keeping the IRQ asserted.
2. Configure the interrupt mode to Change from Read . When the interrupt is asserted, inside the ISR, read from the PRTxDR register and this will immediately de-assert the IRQ line.
3. To address extreme corner cases where another GPIO asserts the IRQ line before the interrupt type of the present GPIO is changed, keep a copy of all the pin states in a RAM variable. Every time a GPIO interrupt is triggered, check the state of all the pins and compare this with the previous state stored in the RAM variable. This way, all the pins that changed state can be detected. Before exiting the ISR, update the RAM copy with the present state of the GPIO pins.
Apart from the above techniques, if you have free digital blocks or analog blocks left, you can also route the GPIO pin to a digital buffer and enable the interrupt of that digital block, or connect the GPIO to a comparator and enable the interrupt of the comparator bus. This will provide dedicated interrupt vectors to the GPIOs.