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Connect VREF to a pin in PSoC4 | Cypress Semiconductor

Connect VREF to a pin in PSoC4

 
My colleague Mike brought me an interesting problem.
 
In some applications it may be required to bring out PSoC s internal VREF to an external pin for example, as analog ground, or as reference to an external analog circuit.  In PSoC1, this can be achieved by using the testmux .  This is explained in an article that I wrote a few years back My Favorite PSoC Hacks, Connect AGND to a pin.  In PSoC3 and PSoC5, VREF may be connected as input to an OpAmp buffer and routed to an external pin.  
 
But PSoC4 does not have the option to connect the internal VREF to an OpAmp.  How do we bring out VREF in PSoC4 then?
 
As I have explained in a previous article Measuring VDD in PSoC4, PSoC4 has an external VREF bypass on P1.7.  When enabled, an external bypass capacitor of 1uF connected to P1.7 reduces noise on VREF.  Below picture shows the block diagram of the SAR Reference block.  Turning on the switch (outlined with the red box) routes VREF to P1.7.  The switch is controlled by Bit7 of SAR_CTRL register.
 
 
This can be done either by using the ADC configuration wizard or in firmware by direct register write to the SAR_CTRL register.  Once VREF is brought out to P1.7 using either of these methods, P1.7 then can be connected to the input of an OpAmp buffer and the output of the buffer connected to a pin.  Though this sounds straightforward, each of these methods has some implementation issues.  Let us look at these issues and the solutions.
 
Some engineers prefer to keep the design clean and simple by avoiding custom register writes in firmware to enable features.  As I too like to keep things simple here is the first option.
 
Option-1 VREF on P1.7 through ADC configuration window
 
Let us first enable external VREF bypass by selecting Internal 1.024V, bypassed option for the VREF parameter in the ADC configuration window. 
 
 
Let's then place an OpAmp configured as a Follower .  Let's connect an analog pin named VREF_IN to the input of the OpAmp and another pin VREF_OUT to the output.
 
 
The next step is to assign P1.7 to VREF_IN pin and any other port pin to VREF_OUT.  Now we have a problem.
 
 
In the pin assignment table in .cydwr, there is a pin ADC_SAR_Seq_1:Bypass , with the only option as P1.7.  Once P1.7 is assigned to the Bypass pin, it is not possible to assign P1.7 to VREF_IN.  The simplest solution to this problem is use another pin, say P1_5 as VREF_IN and externally connect P1_7 and P1_5.
 
However, this has a disadvantage of using an extra pin and does not work with designs with shortage of IOs.  The next option is for these designs.
 
Option-2 VREF on P1.7 with register write
 
Let us choose Internal 1.024V as VREF in the ADC configuration window.
 
 
This will let us choose P1_7 as VREF_IN input to the OpAmp buffer.
 
 
All we need to do now is to enable VREF bypass by writing to the ADC s configuration register.  Following code does this.
 
uint32 SARControlReg;
 
/* Enable reference bypass */
SARControlReg = CY_GET_REG32(CYREG_SAR_CTRL);
SARControlReg |= 0x00000080;
CY_SET_REG32(CYREG_SAR_CTRL, SARControlReg);
 
This will enable the VREF bypass switch in the SAR ADC block and will bring out VREF to P1.7.  Start the OpAmp, and buffered VREF should be available on the pin connected to OpAmp s output.
 
There is just one more problem to solve.  Notice the max ADC sample rate from the ADC configuration window in Option#1 and Option#2.  When the reference is selected to Internal 1.024V, bypassed , the maximum possible ADC sample rate is 1.125Msps for a single channel ADC.  When the reference is set to Internal 1.024V the maximum possible sample rate is only 100ksps.  For ADC sample rate above 100ksps, external VREF bypass is a must.  Though we use external bypass, as we do this in firmware, the ADC wizard does not know this and does not allow you to select a higher speed.
 
Then how do we get a higher sample rate from the ADC?
 
Option 2a VREF on P1.7 with register write and high ADC sample rate
 
In this method, instead of letting ADC configuration wizard to select the ADC clock, we will set the clock.  In the ADC configuration window, select the Clock Source parameter to External .
 
 
This will add a pin named aclk to the ADC component.  Now drag a Clock component from the components catalog (under the System folder) and connect this to ADC s aclk input.
 
 
In the clock configuration window, select HFCLK as the clock source, and set the clock to 1MHz.  
 
 
If we set the clock to a higher value in the clock configuration, next time when we open ADC configuration wizard, the wizard sees the value of the external clock to be more than 1MHz and will throw an error.  We will fool the wizard by setting the required clock in firmware. For example, if we need an ADC clock of 2MHz then we require a divider of 12.  Use the following code in firmware to set the divider.
 
ADC_Clock_SetDivider(12);
 
Now we got VREF on an external pin, without having to waste an extra IO, and also can run the ADC at a higher sample rate without offending the ADC wizard!
 
Choose the option that best suits your application and get a buffered VREF to an external pin.

Comments

mfroberts's picture

There is another way which I have implemented and tested. Configure the ADC with 1.024V bypassed on P1.7 and make the Opamp Input connection in firmware

CY_SET_REG32(CYREG_CTBM_OA1_SW, 0x10); // Manually connect P1[7] to Opamp_Vref positive terminal

graa's picture

Hello Roberts, Yes. That is a good option as well. Thanks for pointing this out. Best Regards.

DrJeff's picture

Thank you Ganesh for a useful workaround.

Have successfully implemented this but found that it was necessary to adjust the power level of the ADC using bits 24 & 25 in the control register CYREG_SAR_CTRL.

I could not find direct definitions of this but by examining the Macro ...ADC_DEFAULT_POWER I have inferred the following for a desired clock frequency of fClk:

fClk > 4.5MHz bits 25 and 24 equal 0

4.5MHz > fClk > 2.25MHz bit 25 = 0, bit 24 = 1

fClk < 2.25MHz (the way it will be set up in the above scheme) bits 25 and 24 equal 1

Hence, referring to your code snippet adjacent to "SARControlReg |= 0x00000080;" :

fClk > 4.5MHz add the following line:

SARControlReg &= 0xFCFFFFFF;

4.5MHz > fClk > 2.25MHz  add the following line:

SARControlReg &= 0xFDFFFFFF;

fClk < 2.25MHz : No change required.

Hope this is useful to someone :).

 

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