SAR vs. ΣΔ | Cypress Semiconductor

SAR vs. ΣΔ

Several months ago, I worked on a project that involves analysis on the SAR ADC architecture, which got me obsessed on the various implementation from different vendors. I enjoy calculating the single and multiple channle converstion time for diffrent resolution settings for hours. Then one night, I had a dream about the SAR ADC.

Yes, as much odd as it sounds, I did dream of it. When I woke up, all I remember is that some thing about the SAR upset me for big time. I even held fists full of emotions in my dream. Insanity? Yes. Stuff like that definitely put me out of 3 sigma in the normal human being behavior statistics, but the good side is that dream inspired me to team up with our senior apps engineer Andrew Siska to write this article: "Golden Gloves" A/D Converter Match: Successive-approximation register vs. sigma-delta topology":

In one corner, the current champion successive-approximation register (SAR) analog/digital converter (ADC); in the opposing corner, a relative newcomer to the A/D conversion scene, the sigma-delta (ΣΔ) ADC. This will be a seven-round fight to the finish, with judges awarding points in the following categories:

   1. Conversion Accuracy
   2. Speed of Conversion
   3. Linearity of Strikes
   4. Conversion Accuracy in the Low and High Side Corners
   5. Differential Non Linearity
   6. Integral Non Linearity
   7. Quantization Error

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You can access the full article at here.

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