The yawn of memory | Cypress Semiconductor
The yawn of memory
June 03, 2010
Everyday I’m reminded by about every design engineer and salesman I talk to that the memory IC business is (yawn)… a bit boring.
When one is in the depths of creating a new system design with complex interfaces to the outside world, intricate algorithms that must run error-free on that new controller, marketers’ changing demands, feature creep finding its way in to every corner of the project, and a management chain that needs it all done faster than ever with less people and less money, well, let’s just say, that memory decisions seem, indeed, relatively boring.
Our datasheets can be mastered in a day, even if you use our fastest interfaces. Our block diagrams are usually just one big square in the middle surrounded by some innie’s and outie’s.
My counter to these most obvious of observations is that Cypress puts a lot of money and sweat and analysis and commitment into our memory products just so that they can be a boring, and even a forgotten, part of your design. And if you, the designer, will make the Cypress decision early (and often) with regards to your memory needs, then we are happy to remain as that forgotten, but critical, part of your masterpiece.
Products like our nvSRAM that combines SRAM and non-volatile, our FIFO’s, our QDR, etc. can add even more simple (and boring) features that will further free you up for the fun and interesting stuff.
And the best thing about Cypress memories is that you can pass the gift forward: we will also become a boring part of your buyers’ life and your contract manufacturer’s life, because we are a big supplier with superb quality that works very hard to be on the BEST SUPPLIER lists.
Sometimes, it is nice to be boring.
Until next trip, Grant