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Don't let your filter design package throw your bits away! | Cypress Semiconductor

Don't let your filter design package throw your bits away!

When customers discover the Digital Filter Block in PSoC3 and PSoC5, they sometimes ask if they can import their own filter coefficients.  Because we've been updating the FILT component in PSoC Creator to give it IIR filter capability in the next release, I've been taking a look at the tools people use to create IIR digital filters.  And quite frankly, it's not a pretty sight!  All the digital filter design environments I've seen so far seem to have come into existence without any contact with someone who has to design and manufacture good filters as a "day job".

If you've ever designed a high order analog active filter from a cascade of 'biquad' sections, you'll probably have discovered how important it is both to get those sections in the right order and to get the individual gains set properly.  It's the only way to avoid premature overload (sometimes hard to detect when it occurs internally) and excessive build-up of noise.

It seems like many digital filter designers are unaware that the issues of hidden overload and noise build-up apply just as much to digital IIR filter cascades as they do to analog filters.  In fact, although the output noise power of an analog filter falls with reducing cutoff frequency, that of a digital filter actually increases!  It's to do with the magnification of the inevitable quantization of the filter calculations, and I'll put a Filter Wizard piece out on the web on that soon.

These days, the presumption is that you'll have enough spare bits both above and below your working dynamic range that you can completely ignore this.  But these bits aren't free, either in area or power consumption.  In practical, commercially viable systems, you often have to push the hardware you can afford close to its theoretical limits to get the job done.  The PSoC3/5 DFB is a 24bit fixed-point engine, but you should still use such capacity wisely to have a chance of achieving respectable performance in your application.

So, I've put a lot of effort into ensuring that the IIR filters that the next Creator FILT component will generate are carefully sequenced and gain-adjusted to get the best (or close to the best, at least!) dynamic range possible, for any given response shape and cut-off frequency.  Low-frequency filters in particular benefit from this.  Internal safety margins are set to permit the worst case digital input signals - signals that are highly unlikely to originate from any physical system through a sampling process.  DC offset buildup - sometimes a problem with carelessly implemented IIR filter code - has been eliminated.  So, if you want to use any of the IIR filter types that we'll be supporting in the next release, please do use the Creator internal routines to do the design.  Don't assume that because you paid $10k for the math package you use, that it will do a better job - because it quite possibly won't!

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