Self Dithering PWM | Cypress Semiconductor
Self Dithering PWM
Our standard PWMs are made by continuously decrementing a register in a datapath (A0). The compare register is used to detect when the count is below some compare value (D1) and set an output high. For a 256 count PWM it can be implemented with a single instruction register of the datapath. For a compare value of 50, the periodic output stream would be 206 low, followed by 50 high. The frequency would by clock / 256.
If the output frequency is too low and you can t increase the clock, then convert to a self dithering PWM. If instead I change the datapath to continuously subtract 3 from the A0 and keep the same compare value of 50, the periodic output stream is:
69 low, 17 high, 68 low, 17 high, 69 low, 16 high
The output frequency is 3 * clock / 256.
Changing to subtracting 5 while keeping the same compare value, gives the periodic output stream:
42low, 10high, 41low, 10high, 41low, 10high, 41low, 10high, 41low, 10 high
The output frequency is 5 * clock / 256.
And so on. If the value n is a relative prime to 256 (odd) and less than 128 is continuously subtracted from a register, the stream has n pulses and an output frequency of n * clock / 256.
This will also work from 16, 24, and 32 bit PWMs. A 16bit PWM with a 24MHz clock has an output frequency of 366Hz. Change it to a self dithering PWM with n = 137 and you have an output frequency of 50.2kHz, but keeps a dithering resolution of 16 bits.
I never would have figured this out if datapaths didn't make it easy to build and try out.