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Dave Van Ess, Maker of Fine Buggy Whips | Cypress Semiconductor

Dave Van Ess, Maker of Fine Buggy Whips

 While looking at Karnuagh maps, I figured a very clever way to reduce logic when the map has a sparse distribution of diagonal entries.  I worked on it for a couple of hours till I realized that people don t reduce logic anymore.  They let the computer do it!  Oh well.  I came up with a cool method of making state machines with T flip flops and then I realized that Verilog is set up to easily work with D flip flops. T flops are really cool and I don;t understand why they are not appreciated.

Comments

Bob Marlowe's picture

Here is a present for you: A T-flip flop with an asynchronus reset You may use it in any design.

module T_FF (input Clk, input AR, output reg Q);
always @(posedge Clk or posedge AR)
if (AR) Q <= 1'b0;
else Q <= ~Q;
endmodule

Comes in small and handy, just needs a symbol to have it placed anywhere you like

Stub for 6132621's picture

Yes but it is a module and you access it through its variables. For a D flip flop I just declare it to be a reg.

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