Aerospace & Defense | Cypress Semiconductor
AN4011 provides an overview of Standard Synchronous, NoBL, QDR®-II/II+, QDR-II+ Xtreme, DDR-II/II+, DDR-II+ Xtreme and QDR-IV SRAM's. Cypress currently manufactures several major Synchronous SRAM architectures. The purpose of this application note is to provide a means to determine which architecture is right for a particular application. A brief description of each architecture and comparison by address/data relationships and performance characteristics is also included.
Cypress Quad Data Rate (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 Gbps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking, termination techniques and reference design for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.
High speed source synchronous semiconductor devices rely on clock synthesis circuits (DLL - Delay Lock Loop / PLL -Phase Lock Loop) to mitigate on die clock skews. The 72-Mbit RHQDRII™+ SRAM uses a DLL to ensure output data and echo clocks (Strobe) are edge aligned and de-skewed with respect to the source clock. However, all DLLs/PLLs require a certain number of clock cycles to attain “lock” during which the device will not reliably operate. This application note discusses the required steps necessary to effectively transition between maximum performance and power saving modes with proper DLL operation.
AN80555 application note describes the architecture and timing details of a RHQDR® II+ memory interface controller implementation for Cypress's Radiation Hardened QDRII+ SRAMs. The accompanying synthesizable reference design targets Xilinx Virtex-5QV family of FPGA devices.
Software and Drivers
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