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AN34359 - PCB Layout Guidelines for West Bridge™ Generation A Peripheral Controllers in Wafer Level Chip Scale Package | Cypress Semiconductor

AN34359 - PCB Layout Guidelines for West Bridge™ Generation A Peripheral Controllers in Wafer Level Chip Scale Package

Last Updated: 
Dec 14, 2017
Version: 
*E

The West Bridge™ peripheral controllers support high-speed USB as well as mass storage access and are available in a wafer level chip scale package (WLCSP) with 81-balls. The size of this package is less than 4 x 4 mm with a 0.4 mm pitch. This application note discusses the PCB layout guidelines for West Bridge controllers in the WLCSP.