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Fractional Clock Dividers with PSoC 4
Jun 10, 2013
By Bradley Budlong

One of the enhancements to clock generation that was introduced with PSoC 4 is the ability to have fractional clock dividers. By default all the clock dividers are integer clock dividers. For PSoC 4 that means that you can generate a clock whose frequency is the frequency of the High Frequency Clock (HFCLK) divided by a 16-bit integer.  For small dividers that can result in large jumps between adjacent available clock frequencies.  For example if HFCLK is running at 48 MHz, then the available clocks are 48 MHz, 24 MHz, 16 MHz, 12 MHz, ... If you want a clock that is 14 MHz, then you would need to run HFCLK at a multiple of 14 MHz (14, 28, or 42 MHz). In some cases that approach works fine, but it also changes all the other dividers in the system. An alternative solution is to divide by a fractional amount. PSoC 4 supports division by a 16 bit integer (for fractional dividers this must be at least 2) and a fraction which is a multiple of 1/32nd.  In this example you can get close to 14 MHz by dividing by 3 14/32 which yields a frequency of 13.96 MHz. Fractional dividers do however introduce jitter in the clock, so it is important to understand how they work and when you might want to use them.

The first step to understanding fractional clock dividers is to understand integer dividers. In PSoC the clock dividers are implemented off of the source clock rising edge. If the integer divider is even, then a 50% duty cycle clock is generated with the clock low for half the divider value clock periods and the clock high for the same amount of time. Here is a picture of a 3 MHz HFCLK being divided by 4 to produce a 750 kHz clock.

 

 
With the tolerance of the IMO on my specific device the scope measures the frequency at 752 kHz.  The clock is high for two clocks and then low for two clocks.
 
For an odd divider it is not possible to generate a 50% duty cycle using only the rising edge of the source clock. For the case of an odd divider the high pulse width of the generated clock will be one period longer than the low pulse width. That is shown here with the clock being divided by 3.
 
 
In this case the low pulse width is one clock period and the high pulse width is two clock periods.
 
Now I'll turn our attention back to the fractional clock divider and a usage example. In this example I want to run HFCLK at 3 MHz to save power, but I want to run a UART at 115,200 baud. By default the UART is 8x oversampled, so the desired clock is 115,200 * 8 = 921.6 kHz. With integer dividers the best that can be done is 1 MHz which is 8.5% too fast.  That will result in transmission errors. Instead I can provide the UART with a clock from a clock component (select external clock in the UART component) and check the box to have Creator generate a fractional clock as shown here in the clock component customizer.
 
 
Here are the two clock divider possibilities shown in the clock design wide resoruces display with an integer divider resulting in a 1 MHz clock (8.5% error) and with a fractional divider resulting in a 923.077 kHz clock (0.16% error). Creator shows this divider as 3 8/32 or 3.25.
 
 
The way that a 3.25x clock divider is implemented is by dividing by 3x for some periods and 4x for other periods, with the average being 3.25x. In this case the repeating pattern will be (3, 3, 3, 4). That is shown in the following scope capture. Note that the first three periods are divided by 3 and then the next is divided by 4.
 
 
The way this is implemented in the device is to divide by the smaller divider and then extend the high pulse width by one clock cycle periodically. As you can see the low pulse width is the same width as the 3x integer divider (1) and the high pulse width is either the same as the 3x divider (2) or one more (3). In hardware this is implemented by a 5 bit counter which increments by the number of 1/32nds. In this case that is 8. Each time the counter overflows the high pulse is extended by a single cycle. In this case the 8 goes into 32 evenly, so the incrementing pattern is simply (0, 8, 16, 24, 32, 0, ...) with the counter overflowing every 4 times. This approach works with any fraction, but fractions that don't divide evenly will have a longer repeating sequence. For example 15/32 has the sequence (0, 15, 30, 13, 28, 11, 26, ...) and each time it rolls over the high pulse is extended by one cycle.
 
Fractional clock dividers work very well for a UART. In the case of a UART the average frequency is important and the jitter in the clock is not critical. In this particular example since the UART is 8x oversampled the distance between samples turns out to be an integer number of HFCLK cycles (8 * 3.25 = 26 cycles), but even if it hadn't come out evenly the fractional clock divider would be a good choice. For other applications the jitter on the clock signal may not be acceptable. Also, only some of the clock dividers support fractional division. The current PSoC 4 devices have 12 clock dividers and 3 of those 12 support fractional clock division. When you do need a specific output frequency that you can't get with the integer dividers, consider using the fractional clock dividers and evaluate the ability of the circuit to handle the resulting clock jitter.
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Comments:
dvorakvik wrote:
Tue Jun 11 01:06:38 AM
dvorakvik wrote:
Perfect solution for the USART external clock when using "round" external oscillators e. g. TCXO 40.000000 MHz. 
For PSoC4 clock 40 MHz, oversampling 12 and 115200 Baudrate the fractional divider is 20 + 30/32 = 1.382 MHz

Many thanks for this article.
Tue Jun 11 06:41:25 AM
jesusantoniocard wrote:
Hello Sensei.
Excellent explanation about this topic, right now i am exploring the psoc 4   family, it has interesting features to use.

best regards,

Jesus Antonio.
Thu Jun 13 22:45:24 PM
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