Datapath-based designs can offload CPU tasks to increase the efficiency of components. This application note describes the development process step by step. You also will learn how to use the PSoC Creator Datapath Configuration Tool to create, view, and modify datapath instances in Verilog files.
Introduction
Have you maxed out your CPU bandwidth? PSoC 3 and PSoC 5LP UDBs can lighten the load on your CPU by creating intelligent custom peripherals. The datapaths in those UDBs can be used to create sophisticated multiprocessor-based designs.
Many PSoC customers have experience writing HDL code for CPLDs or FPGAs. PSoC 3 and PSoC 5LP support Verilog for PLDs. However, PSoC 3 and PSoC 5LP PLDs are smaller than full-fledged CPLDs or FPGAs, and many designs are too large for PSoC 3 and PSoC 5LP. PSoC’s unique datapath modules remove this obstacle by integrating one or more small 8-bit processors into PLD-based designs.
Notes:
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Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
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Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
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For PSoC 5 project and related document, please download file AN82156_Archive.zip.
Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:
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AN82156.zip is used with PSoC Creator 2.1 SP1
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AN82156_Archive.zip is used with PSoC Creator 2.1/2.0
The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
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