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AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details

Last Updated: 12/02/2012
Version: *A

AN80555 details the implementation and timing details of the RH QDR®II+ Interface Controller targeted for the Xilinx Virtex-5QV family of devices. The given reference design example uses built-in Virtex-5QV structures to achieve an aggregate data throughput of 36-GB per second.

Introduction

RH QDR®II+ Memory Controller contains the logic necessary to read from and write to RH QDRII+ SRAM memory. Its primary function involves synchronizing the Single Data Rate SDR (System Logic) and the Double Data Rate DDR (RH QDRII+ memory) data domains.


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Spec No: 001-80555; Sunset Owner: SZZX; Secondary Owner: WIA; Sunset Date: 03/26/13

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