18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
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No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
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Supports up to 133-MHz bus operations with zero wait states
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Pin-compatible and functionally equivalent to ZBT™ devices
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Internally self-timed output buffer control to eliminate the need to use OE
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Registered inputs for flow through operation
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Byte write capability
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3.3 V/2.5 V I/O power supply (VDDQ)
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Fast clock-to-output times
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For more, see pdf
Functional Description
The CY7C1371DV33 is a 3.3 V, 512 K × 36 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371DV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.
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