72-Mbit (2 M × 36) Pipelined DCD Sync SRAM
Features
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Supports bus operation up to 250 MHz
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Available speed grade is 250 MHz
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Registered inputs and outputs for pipelined operation
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Optimal for performance (double cycle deselect)
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Depth expansion without wait state
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3.3 V core power supply (VDD)
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2.5 V and 3.3 V I/O operation
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Fast clock to output times
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For more, see pdf.
Functional Description
The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
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