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AN47994 - Interfacing TI OMAPV1030 Processor to Cypress West Bridge® Antioch™

Last Updated: 01/21/2013
Version: *A

Cypress West Bridge® Antioch™ device provides high speed USB peripheral and mass storage control capabilities to the system processor through its host processor port. This application note presents a system example of interfacing a TI OMAPV1030 baseband processor to an Antioch device, using Antioch’s Pseudo-CRAM processor-port (P-port) interface.

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    File Title Language File Size Last Updated
      AN47994.pdf English 218 KB 08/17/2011
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Spec No: 001-47994; Sunset Owner: DBIR; Secondary Owner: HBM; Sunset Date: 02/17/12
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