High speed source synchronous semiconductor devices rely on clock synthesis circuits (DLL- Delay Lock Loop / PLL – Phase Lock Loop) to mitigate on die clock skews. The 72-Mbit RHQDRII™+ SRAM uses a DLL to ensure output data and echo clocks (Strobe) are edge aligned and de-skewed with respect to the source clock. However, all DLLs/PLLs require a certain number of clock cycles to attain “lock” during which the device will not reliably operate. This application note discusses the required steps necessary to effectively transition between maximum performance and power saving modes with proper DLL operation.
|