AN68174 - Migrating from Serial Peripheral Interface (SPI) EEPROM to SPI nvSRAM
Last Updated: 06/12/2012
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Version: *B
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Serial SPI EEPROM devices were frequently used in the past for nonvolatile storage of data. However, their low writing speed and limited endurance cycle causes bottleneck when used in designs that need frequent write updates to the nonvolatile memory at the bus speed. Many system designers have tried to solve endurance problems by using wear-leveling techniques to increase effective endurance cycles at the cost of increasing EEPROM density and software overheads. Other designers have taken a buffer memory approach in which the system saves data only at power down or power fail conditions using a reliable backup power source. Both of these approaches have been proven to be expensive solutions because of increased BOM cost, board area, processor I/O usage, design complexity, and software overheads.
This application note provides design guidelines for migrating from SPI EEPROM to SPI nvSRAM. More...
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Related Application Notes:
Domain Tags: Serial, SPI, Non Volatile Memories, non-RTC
Related Knowledge Base: Data Retention, HSB, Migration Path, nvSRAM, Serial, SPI, Vcap, RECALL, HOLD
Spec No: 001-68174;
Sunset Owner: ZSK;
Secondary Owner: PSR;
Sunset Date: 11/11/11
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