FSK is the modulation cornerstone of a number of digital data transmission systems. This application note provides a detailed implementation of FSK generator with very low distortion and zero CPU (M8C core) run-time usage. The design is demonstrated at 1200 Hz and 2200 Hz, Bell 202 standard.
This AN also talks about the method to reduce the 3rd and 5th harmonics by using a dead band PWM generator and a band-pass filter.
In order to be able to understand the functionality better, following pre-readings are suggested:
AN2168: Understanding switched capacitor filters - Discusses how low pass, band pass and notch filters can be implemented using switched capacitor blocks.
KB Article: Generation of non-overlapping signals using dead band PWM generator.
Example Project |
Supported H/W and S/W |
Supported PSoC1 Devices |
|
PSoC Designer Version |
H/W Kit |
CY8C20xxx |
CY8C21xxx |
CY8C22xxx |
CY8C23xxx |
CY8C24xxx |
CY8C27xxx |
CY8C28xxx |
CY8C29xxx |
|
Yes |
5.1 |
CY3210-PSoCEVAL1 |
|
|
|
|
x23A, x94 |
x43 |
x |
x66 |
|