Cypress Perform

Home > Documentation > Component Datasheets
EZI2C Slave 1.80

Last Updated: 12/24/2012
Version: 1.80
PSoC® Creator™ Component Datasheet

Features
  • Industry standard NXP® I2C bus interface
  • Emulates common I2C EEPROM interface
  • Only two pins (SDA and SCL) required to interface to I2C bus
  • Standard data rates of 50/100/400/1000 kbps
  • High level APIs require minimal user programming
  • Supports one or two address decoding with independent memory buffers
  • Memory buffers provide configurable Read/Write and Read Only regions
 Symbol Diagram

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification.The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.
 

Required Software: PSoC Creator v1.0 Beta 5 and above 

这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时，我们强烈建议您参照英文版本。

これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。 最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.




Related Files


Spec No: None; Sunset Owner: MEH; Secondary Owner: GDK; Sunset Date: 05/19/13
Rate Component Da..

Related Pages