Cypress Perform

Could you do a post on how to do a double buffer with the FIFO and DMA? I think users would like to see how a double buffer (ping pong buffer) scheme would work in PSoC 3/5 hardware.

I could certainly do that.  Could you describe a little more about the kind of thing you'd like to see?  For example if it is fixed length data blocks and you just want them to alternate back a forth between two buffers, then that is simple to implement.  You would need to know which buffer to use in software (likely use an interrupt), but otherwise this is just two TDs.

There are three major areas of PSoC that could use some explanation (in my opinion):

1) Ping Pong Buffering. For example, a sensor collects data and the DMA forwards it into buffer A, the program then switches to buffer B to fill. Essentially this is a traditional ping pong buffer as you described.

2) External clocks and digital speeds. My understanding is that the PSoC can only handle up to 33 MHz external signals. however, what happens to the 67MHz & 80MHz limits of the PSoC 3&5? Can they not handle these signals in the UDB? For example, say I have an external 60 MHz clock that is a synchronous data transmission clock. Can I not use this with a sync component?

3) Where are we with EMIF?

Thanks. The blog is really helpful.

Thanks for your comments Dan.  I'll try my best to respond to these 1) A ping pong buffer is straight forward to implement with PSoC 3/5.  The chained structure of the TDs fits well with this construct.  In its simplest form you would have two TDs with one for each of the two buffers.  These would be chained together in a loop.  The important part is coordinating with the CPU.  You want to use the TERM_OUT capability that can optionally be generated at the end of a TD.  As long as you are certain not a miss an interrupt, then the CPU will know which buffer has been filled and be able to toggle between the buffers.  This concept can also be expanded to support any number of buffers.  I've used this also with a continuous stream of data placed in a circular buffer.  In that case the interrupts are used to keep track of the fill level.  2) The output frequency of the GPIOs is limited to 33MHz, but the input frequency is limited to 67MHz.  That means that you could bring in a higher frequency clock signal, but there isn't tight control between an input signal that is brought in as a clock and an input signal that is brought in as data.  That would make handling high speed source synchronous interfaces difficult with PSoC.  Typically the data interfaces with PSoC will want to be sampling using the opposite edge of the clock from the clock edge that changes the data.  The MASTER_CLK/BUS_CLK in PSoC when it is operating at higher speeds is generally created by the PLL.  For example you can take a 3MHz IMO clock or 12MHz Crystal and have the PLL create a 67MHz clock from it.  Then that is the clock that runs the system.  The chip is able to handle signals across the full speced operating range, so you can use 67MHz clocks in the UDBs.  You will however find that many functions that you would want to implement with a UDB will not be able to meet timing at that speed.  That depends on the level of complexity of the function.  Refer to the component datasheets for an expectation of performance and the STA report for the timing for your specific design.  You can use the Sync component with any signal, but you will need a clock of at least 2x the rate of the incoming signal in order to sample the signal and not loose edges.  3) The EMIF is supported in the production PSoC3 silicon (along with ES3) that is now available.  Support in PSoC Creator is available starting with the 1.1 release coming in Q3.  The PSoC5 device will not have EMIF support.  That feature is being removed from the datasheet.