1:2 LVPECL Fanout Buffer
Features
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One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
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Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
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20-ps maximum output-to-output skew
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480-ps maximum propagation delay
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0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
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Up to 1.5-GHz operation
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8-pin SOIC or 8-pin TSSOP package
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2.5-V or 3.3-V operating voltage
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Commercial and industrial operating temperature range
Functional Description
The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.
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