AN66311 - Timing Recommendation for Byte Enables and Chip Enables in MoBL® SRAMs
Last Updated: 09/11/2012
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Version: *C
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| AN66311 provides timing recommendations for the use of byte enable pins (BHE and BLE) and chip enables (single or dual, as applicable) in select Cypress MoBL® SRAMs. Note that the datasheet should be read before implementing timing recommendations mentioned in this document. |
This Application note explains a particular timing condition in SRAM accesses that could cause an unexpected behavior of the device. The condition involves Address lines and Chip Enable or Byte Enable lines. A workaround is also suggested in the application note. A brief pictorial representation is shown below; please read the application note for a detailed explanation.
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Related Application Notes:
Domain Tags: Volatile Memories, Async
Related Knowledge Base: SRAM, Timing, BHE / BLE, Async, uPower, MoBL
Spec No: 001-66311;
Sunset Owner: NILE;
Secondary Owner: AJU;
Sunset Date: 07/12/11
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