18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Features
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18 Mbit density (2 M x 8, 1 M x 18)
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333-MHz clock for high bandwidth
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Two-word burst for reducing address bus frequency
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Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
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For more, see pdf
Functional Description
The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock.
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