Cypress Perform

Home > Documentation > Component Datasheets

Interrupt

Last Updated: 11/13/2013
Version: 1.70

PSoCĀ® Creator™ Component Datasheet

Features

  • Defines hardware-triggered interrupts
  • Provides a software method to pend interrupt
Symbol Diagram

General Description

The Interrupt component defines hardware triggered interrupts. It is an integral part of the Interrupt Design-Wide Resource system (see PSoC Creator Help, Design-Wide Resources section).

There are three types of system interrupt waveforms that can be processed by the interrupt controller:

  • Level – IRQ source is sticky and remains active until firmware clears the source of the request with an action (for example clear on read). Most fixed-function peripherals have level-sensitive interrupts, including the UDB FIFOs and status registers.
  • Pulse – Ideally, a pulse IRQ is a single bus clock, which logs a pending action and ensures that the ISR action is only executed once. No firmware action to the peripheral is required.
  • Edge – An arbitrary synchronous waveform is the input to an edge-detect circuit and the positive edge of that waveform becomes a synchronous one-cycle pulse (Pulse mode).

这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时,我们强烈建议您参照英文版本。

これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。 最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.




Related Files


Spec No: 001-85137; Sunset Owner: HMI; Secondary Owner: POA; Sunset Date: 06/15/20

Rate Component Da..

Related Pages

Spec No: 001-85137; Sunset Owner: HMI; Secondary Owner: POA; Sunset Date: 06/15/20