Cypress Perform

In previous posts I've shown how to use DMA with PSoC 3 and PSoC 5.  I've also shown where to find training materials on building your own Verilog components.  However, you really need access to the FIFOs in the datapaths to build many applications that use DMA.  Support for building datapath based components isn't available until the next version of PSoC Creator (Beta 5).  So how can you take advantage of datapath FIFOs without needing to program a datapath?  A component that interfaces to a datapath FIFO is the natural solution.

I've provided a component that takes a parallel 8-bit input and sends it into the datapath FIFO.  In future posts I'll provide components that are both 8 and 16 bits wide along with providing components that operate with the FIFO in the opposite direction.  To prove out the operation of this first component I've included the following project:

This project has two components.  The FIFOIn8 component is the component that gives you access to the datapath FIFO.  On each clock (clk) if the enable signal (en) is high, then the data is sampled and placed into the FIFO.  The status provided is an indication of whether the FIFO is currently full and a DMA request that triggers the DMA if the FIFO is not empty.  The DMA must be operated in a level triggered manner (refer to the main.c example code for how to set the DMA into that mode).  The second component is the Count8 component.  This is simply an 8 bit counter that counts up whenever the enable signal is high.  By using the FIFO full flag to throttle the counter (enabled when the FIFO is NOT full) to the speed that the DMA can remove data from the FIFO, the result is a continuous stream of incrementing bytes into the FIFO.

To observe how this operates, bring the design up in the debugger within PSoC Creator.  Set a Watch on the buffer (buf[]).  Initially the buffer will be filled with all 0's.  Allow the code to run and then pause the code execution.  Now the debugger will update the display of the buffer and you will see that it contains the sequential values that have been DMAed in from the FIFOIn8 component.

This component can be used anywhere that you want to capture a stream of values.  For example if you want to capture a stream of values coming in on the pins of the device, those pins could be connected to the data lines of this component and the values could be captured to SRAM or the data transferred to a peripheral.  The datapath FIFO provides a 4 entry buffer to allow time for a DMA response and it also provides the appropriate signals to trigger the DMA.

The design InOut8 Project can be downloaded and run on any PSoC 3 based development kit.  This same code will also work with the upcoming PSoC 5 development kits.