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AN61345 - Implementing an FX2LP™- FPGA Interface

Last Updated: 01/18/2013
Version: *G

AN61345 provides a sample project to interface an FX2LP™ (CY7C68013A) with FPGA.

The interface, described in a sample implementation, adds High-Speed USB connectivity to applications such as data acquisition, industrial control and monitoring, and image processing. The Project provided with this Application Note is implemented and tested with Xilinx Virtex 5 and Spartan 3E FPGAs.

An FX2LP™-FPGA interface is implemented to add High-Speed USB connectivity for FPGA based applications, such as data acquisition, industrial control and monitoring, and image processing. The FX2LP acts in Slave-FIFO mode and the FPGA acts as the master. This Application Note also gives a sample FX2LP firmware for Slave-FIFO implementation and a sample VHDL and Verilog project for FPGA implementation.

 


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Related Files

    File Title Language File Size Last Updated
      AN61345.pdf English 2 MB 01/18/2013
      AN61345.zip English 8 MB 01/18/2013
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Spec No: 001-61345; Sunset Owner: PRJI; Secondary Owner: HBM; Sunset Date: 06/06/11

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