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AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

Last Updated: 05/07/2013
Version: *H

AN61345 provides a sample project to interface an FX2LP™ with FPGA using Slave FIFO interface. The interface, described in the sample implementation, adds High-Speed USB connectivity to applications such as data acquisition, industrial control and monitoring, and image processing. The project provided with this application note is implemented and tested with Xilinx Spartan 6 FPGA.

An FX2LP-FPGA interface is implemented to add High-Speed USB connectivity for FPGA based applications, such as data acquisition, industrial control and monitoring, and image processing. The FX2LP functions in synchronous Slave-FIFO mode and the FPGA acts as the master. This application note also provides a sample FX2LP firmware for Slave-FIFO implementation and a sample VHDL and Verilog project for FPGA implementation.


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Spec No: 001-61345; Sunset Owner: RSKV; Secondary Owner: OSG; Sunset Date: 06/06/11

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Spec No: 001-61345; Sunset Owner: RSKV; Secondary Owner: OSG; Sunset Date: 06/06/11