Cypress Perform

Verilog is the implementation methodology used to describe the logic that is placed in the PLD portion of the programmable digital architecture used in PSoC 3 and PSoC 5.  This course explains the PLD implementation used and the methodology used to map a Verilog description of digital logic to the physical implementation in the hardware.  The basic constructs used for both combinatorial and sequential logic in Verilog are shown.  The differences introduced by development in Verilog for symbols and parameters is explained.