User Module Datasheet: 6 to 14-Bit Delta Sigma ADC Datasheet DelSigMulti V 1.2 (CY8C28X45, CY8C28X43, CY8C28X52, CY8C28X33, CY8C28X23)
Last Updated: 10/31/2012
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Version: 1.2
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Features and Overview
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6-bit to 14-bit resolution
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2 to 4 channels of synchronized sampling
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Data in unsigned or signed 2’s complement formats
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Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
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Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
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1st Order or 2nd Order modulator for improved signal-to-noise ratio, user selectable
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Input range defined by internal and external reference options
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Requires no digital blocks
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Configuration wizard enables you to easily select between 2, 3 or 4 channels of delta-sigma ADC measurements that are all synchronized with each other
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The internal timer of the decimators allows no digital block use
The DelSigMulti User Module is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs invalidates the first two samples after the change. This DelSigMulti User Module supports up to 4 channels of simultaneous, synchronized deltasigma ADC sampling.
A configuration wizard allows you to easily select the number of analog blocks that are used by each channel and the decimator oversample rate of each channel.
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Spec No: 001-54320;
Sunset Owner: VED;
Secondary Owner: JMY;
Sunset Date: 06/06/11
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