CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM 2-Word Burst Architecture
Last Updated: 01/22/2013
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Version: *P
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72-Mbit DDR II SRAM 2-Word Burst Architecture
Features
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72-Mbit Density (4M x 18, 2M x 36)
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333 MHz Clock for High Bandwidth
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2-word Burst for reducing Address Bus Frequency
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Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz
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Two Input Clocks (K and K) for precise DDR Timing
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Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
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Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
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Synchronous Internally Self-timed Writes
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DDR II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
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For more, see pdf.
Functional Description
The CY7C1518KV18, and CY7C1520KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.
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Spec No: 001-00437;
Sunset Owner: NJY;
Secondary Owner: VIDB;
Sunset Date: 06/06/11
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