User Module Datasheet: Delta Sigma ADC Datasheet DelSig V 1.40 (CY8C29xxx, CYC8C24x94, CY7C64215, CY8CLED04/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52)
Last Updated: 10/23/2012
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Version: 1.40
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Features and Overview
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6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
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Data in unsigned or signed 2’s complement formats
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Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
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Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
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1st-Order or 2nd-Order modulator, user selectable
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Input range defined by internal and external reference options
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Optional synchronized PWM Output
The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.
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Spec No: 001-13432;
Sunset Owner: VED;
Secondary Owner: JMY;
Sunset Date: 06/06/11
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