User Module Datasheet: Delta Sigma ADC Datasheet DelSigPlus V 1.0 (CYC8C24x94, CY8CLED0xD, CY8CLED0xG, CY8C28x45, CY8C28x43)
Last Updated: 10/31/2012
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Version: 1.0
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Features and Overview
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6-bit to 14-bit resolution
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Data in unsigned or signed 2’s complement formats
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Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
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Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
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1st-Order or 2nd-Order modulator for improved signal-to-noise ratio, user selectable
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Input range defined by internal and external reference options
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Requires no digital blocks
The DelSigPlus User Module is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs invalidates the first two samples following the change. Please review the Parameters section prior to module placement.
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Spec No: 001-25679;
Sunset Owner: VED;
Secondary Owner: SNV;
Sunset Date: 10/18/11
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