User Module Datasheet: SPI Master Datasheet SPIM V 3.00 (CY8C20x34, CY8C20x24, CY8C20x66, CY8C20x36, CY8C20336AN, CY8C20436AN, CY8C20636AN, CY8C20xx6AS, CY8C20XX6L, CY8C20x46, CY8C20x96, CY7C604xx, CY7C643xx, CYONS2010, CYONS2011, CYONSFN2051, CYONSFN2053, CYONSFN2061, CYONSFN2151, CYONSFN2161, CYONSFN2162, CYONSFN2010-BFXC, CYONSCN2024-BFXC, CYONSCN2028-BFXC, CYONSCN2020-BFXC, CYONSKN2033-BFXC, CYONSKN2035-BFXC, CYONSKN2030-BFXC, CYONSTN2040, CY8CTST200, CY8CTMG2xx, CY8C20xx7/7S)
Last Updated: 10/15/2012
|
|
|
Version: 3.00
|
Features and Overview
-
Supports Serial Peripheral Interconnect (SPI) Master protocol.
-
Supports SPI clocking modes 0, 1, 2, and 3.
-
Selectable input sources for clock and MISO.
-
Selectable output routing for MOSI and SCLK.
-
Programmable interrupt on SPI done condition.
-
SPI Slave devices are independently selected.
The SPIM User Module is a Serial Peripheral Interconnect Master. It performs full duplex synchronous 8- bit data transfers. SCLK phase, SCLK polarity, and LSB First are available to accommodate most SPI clocking modes. Controlled by user supplied software, the slave select signal is able to control one or more SPI Slave devices. The SPIM PSoC block has selectable routing for the input and output signals and programmable interrupt driven control.
|
这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时，我们强烈建议您参照英文版本。
これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。
最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。
Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.
Spec No: 001-13678;
Sunset Owner: DHA;
Secondary Owner: GDK;
Sunset Date: 06/15/21
|
|