72-Mbit (2M x 36/4M x 18) Pipelined SRAM with NoBL™ Architecture
Features
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Pin-compatible and functionally equivalent to ZBT™
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Supports 250 MHz bus operations with zero wait states
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Internally self-timed output buffer control to eliminate the need to use asynchronous OE
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Fully registered (inputs and outputs) for pipelined operation
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Byte Write capability
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Single 2.5V power supply
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2.5V I/O supply (VDDQ)
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Fast clock-to-output times
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For more, see pdf
Functional Description
The CY7C1470BV25 and CY7C1472BV25 are 2.5 V, 2 M × 36/4 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25 and CY7C1472BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25 and CY7C1472BV25 are pin-compatible and functionally equivalent to ZBT devices.
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