9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
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Pin-compatible and functionally equivalent to ZBT
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Supports 250 MHz bus operations with zero wait states
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Internally self-timed output buffer control to eliminate the need to use asynchronous OE
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Fully registered (inputs and outputs) for pipelined operation
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Byte write capability
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Single 3.3 V power supply (VDD)
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3.3 V or 2.5 V I/O power supply (VDDQ)
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Fast clock-to-output times
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For more, see pdf
Functional Description
The CY7C1354C and CY7C1356C are 3.3 V, 256 K x 36 and 512K x 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.
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