18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
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Supports 133 MHz bus operations
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512K × 36 and 1M × 18 common I/O
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3.3V core power supply (VDD)
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2.5V or 3.3V I/O supply (VDDQ)
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Fast clock-to-output time
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Provides high performance 2-1-1-1 access rate
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User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
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Separate processor and controller address strobes
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For more, see pdf
Functional Description
The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
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