Cypress Perform

Home > Documentation > Datasheets

CY7C1338G: 4-Mbit (128 K × 32) Flow-Through Sync SRAM

Last Updated: 03/27/2014
Version: *M


4-Mbit (128 K × 32) Flow-Through Sync SRAM

Features

  • 128 K × 32 common I/O
  • 3.3 V core power supply (VDD)
  • 2.5 V or 3.3 V I/O supply (VDDQ)
  • Fast clock-to-output times
    • 8.0 ns (100-MHz version)
  • Provide high-performance 2-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed write
  • Asynchronous output enable
  • Offered in Pb-free 100-pin TQFP package
  • “ZZ” sleep mode option
     

Functional Description

The CY7C1338G is a 128 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).


这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时,我们强烈建议您参照英文版本。

これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。 最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。




Related Files

    File Title Language File Size Last Updated
      CY7C1338G.pdf English 619 KB 12/25/2013
    Need help? Ask a question and find answers in the Cypress Developer Community Forums.

    Low/intermittent bandwidth users tip: Firefox and Chrome browsers will allow downloads to be resumed if your connection is lost during download.


Spec No: 38-05521; Sunset Owner: PRIT; Secondary Owner: SZZX; Sunset Date: 06/15/20

Rate Datasheet

Related Pages

Related Parts

Spec No: 38-05521; Sunset Owner: PRIT; Secondary Owner: SZZX; Sunset Date: 06/15/20