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CY7C1327G: 4-Mbit (256 K × 18) Pipelined Sync SRAM

Last Updated: 11/27/2014
Version: *P

4-Mbit (256 K × 18) Pipelined Sync SRAM


  • Registered inputs and outputs for pipelined operation
  • 256 K × 18 common I/O Architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • Provide high performance 3-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • For more,  see pdf.

Functional Description

The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:B], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.


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Related Files

    File Title Language File Size Last Updated
      CY7C1327G.pdf English 780 KB 11/27/2014
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Spec No: 38-05519; Sunset Owner: PRIT; Secondary Owner: SZZX; Sunset Date: 06/15/20