72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
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Pin compatible and functionally equivalent to ZBT
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Supports 200 MHz Bus operations with zero wait states
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Internally self timed output buffer control to eliminate the need to use asynchronous OE
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Fully registered (inputs and outputs) for pipelined operation
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Byte write capability
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Single 3.3 V power supply
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3.3 V/2.5 V I/O power supply
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Fast clock-to-output time
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For more, see pdf
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2 M x 36/4 M x 18/1 M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.
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