High Speed Multifrequency PLL Clock Buffer
Features
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12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation
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Matched pair output skew < 200 ps
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Zero input-to-output delay
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10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines
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Commercial temperature range with eight outputs at 200 MHz
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Industrial temperature range with eight outputs at 200 MHz
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3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs
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Multiply ratios of (1–6, 8, 10, 12)
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Operation up to 12x input frequency
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For more, see pdf
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems.
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