FullFlex(TM) Synchronous SDR Dual Port SRAM
Features
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True dual port memory enables simultaneous access to the shared array from each port
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Synchronous pipelined operation with single data rate (SDR) operation on each port
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Selectable pipelined or flow-through mode
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1.5 V or 1.8 V core power supply
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Commercial and Industrial temperature
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IEEE 1149.1 JTAG boundary scan
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Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
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For more, see pdf
Functional Description
The FullFlex™ dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.
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